1. Field of the Invention
The field of the invention is directed towards Phase Change Memory (PCM) devices. In particular, the field of the invention is directed to the relaxation of stress in PCM devices.
2. Description of the Related Technology
The most recent memory technology to gain widespread acceptance is flash memory. However, as storage and speed requirements increase with each new product generation, flash memory is reaching the end of its ability to keep pace with new demands. The technology can scale up only so far as the processes used to make these chips reach both practical and theoretical limits. Recently, Phase transition random access memory (PRAM) and PCM has attracted great attention due to its nonvolatile memory properties and fast write/read speeds. Furthermore, it has the potential to solve many intrinsic limitations of conventional memory devices such as dynamic random access memory, static random access memory, and flash. The realization of PRAM devices is, however, still limited due to the requirements of small cell size, high scalability, and low power consumption.
The major bottleneck for achieving high density PRAM devices is the large writing currents needed to prepare the system in the amorphous physical state associated with a high resistance reset state and the drift in resistance and threshold voltage leading to data loss and device variability. The reduction of writing currents by reducing the device size is desirable because it can realize faster amorphization of material with less power consumed, enabling fast memory switching speed with high reliability. These challenges motivate the design of device schemes with sublithographic features based on a bottom-up approach using nanowires (NWs) with small diameters.
A PCM cell made of chalcogenide alloy, such as for example a Ge—Sb—Te alloy, utilizes an electrically initiated reversible amorphous-to-crystalline phase change with significant different electrical resistivities. The different phase resistances are used as the two logic states. PCM is also promising for realizing a multi-level cell (MLC) operation because it has a very wide range of resistance across two orders of magnitude. According to the PRAM road map, it is expected that the highest memory densities of PRAM will be comparable to memory densities of conventional memories such as NOR Flash and DRAM in the coming years when MLC operation is fully accomplished. However, in order to realize MLC operation in PCM devices, the temporal drift of the resistance is a major roadblock since it can erase the information that has been written on the device.
In operation, PRAM and PCM devices use electrical current to trigger the structural change. FIG. 1 is a flow chart showing the process by which a PCM device stores data. In step 102 a chalcogenide crystal is provided. A chalcogenide is a chemical compound consisting of at least one chalcogen ion and at least one more electropositive element. All group XVI elements of the periodic table are defined as chalcogens; however the term is more commonly used for indicating sulfides, selenides and tellurides, rather than oxides.
In step 104, an electrical pulse lasting a few tens of nanoseconds in duration melts the chalcogenide at a particular spot. In step 106, when the pulse rapidly tails off, the melted spot's temperature drops quickly and the disorganized atoms freeze in place to form an amorphous phase with high electrical resistance. In step 108, for re-crystallization, the process requires a longer, less-intense current pulse that heats the amorphous spot without melting it. In step 110, energy from the second heating process of step 108 energizes the atoms just enough so that they rearrange themselves into a crystalline lattice, which is characterized by a lower electrical resistance. In step 112, a probe measures the electrical resistance of the spot thus permitting one to distinguish the distinct states of higher and lower electrical resistance as 0 and 1 in binary logic and reads the recorded information.
In September 2006, Samsung announced a prototype 512 Mb (64 MB) device using diode switches. The prototype featured a cell size of only 46.7 nm, smaller than commercial Flash devices available at the time. The high density of Samsung's prototype PRAM device suggested it could be a viable Flash competitor, and would not be limited to niche roles as other devices have been. PRAM appeared to be particularly attractive as a potential replacement for NOR Flash, where the device capacities typically lag behind capacities of NAND Flash devices. Samsung, in their current prototype 512 MB device also reported that their drift coefficients of amorphous resistance in conventional thin-film devices are of the order of 0.04 to 0.108 at room-temperature for a time interval of 103 seconds after a reset pulse.
Intel and STMicroelectronics, demonstrated their own PCM devices at the 2006 Intel Developer Forum and showed a 128 MB device that recently began manufacture at STMicroelectronics's research lab in Agrate, Italy. Intel stated that the devices were strictly proof-of-concept, but they expect to start sampling within months, and to have widespread commercial production within a few years. Intel reported the drift coefficients of amorphous resistance in conventional thin-film devices are on the order of 0.04 to 0.10 at room-temperature for 9 orders of time interval, spanning from time intervals of 10−6 to 103 seconds after the reset pulse.
PCM also may be a promising technology in the military and aerospace industries. PCM memory devices have been introduced by BAE Systems, referred to as C-RAM, claiming excellent radiation tolerance (rad-hard) and latchup immunity. Additionally, BAE claims a write cycle endurance of 108, which will allow it to be a contender for replacing PROMs and EEPROMs in space systems.
In February 2008, Intel engineers, in cooperation with STMicroelectronics, revealed the MLC PCM array prototype. The prototype stored two logical bits in each physical cell, effectively 256 MB of memory stored in a 128 MB physical array. This means that instead of the normal two states, fully amorphous and fully crystalline, an additional two distinct intermediate states representing different degrees of partial crystallization, were also employed, thereby allowing for twice as many bits to be stored in the same physical area on the chip. Also in February 2008, Intel and STMicroelectronics began shipping prototype samples of their first PCM product to customers. The 90 nm and 128 MB (16 MB) product are called Alverstone™.
While PCM devices are being developed to reduce data drift and increase storage, there is still need in the field to develop a PCM device that provides efficient relaxation of stress. This may be accomplished via the development of a PCM device that is able to release its stress upon amorphization via the minimization of reset resistance and threshold resistance.